Regaining a leadership role in semiconductor, microelectronics, and compute technologies has been a strong focus in the United States since the pandemic created supply-chain chaos and disrupted the microelectronics industry. Add in the current geopolitical conditions, and creating a supply of semiconductors that are leading edge, cyber secure, and shipped so as to not get disrupted by outside circumstances is of utmost importance for the future and leadership of the U.S. microelectronics industry. The CHIPS Act has set the wheels in motion to help enable a secure supply of advanced semiconductors on U.S. soil, as well as to focus on future technology development. One of the new organizations that will be formed from the CHIPS Act is the National Semiconductor Technology Center (NSTC), which is chartered with 1) extending America’s leadership in semiconductors; 2) reducing the time and cost of moving from idea to commercialization; and 3) building and sustaining a semiconductor workforce development ecosystem.

The Special Competitive Studies Project (SCSP), a think tank chaired by Eric Schmidt and led by CEO and President Ylli Bajraktari, recently published a report outlining an action plan for how the U.S. can regain its competitive advantage in the microelectronics space. To close the gaps in the domestic microelectronics innovation ecosystem, the SCSP report recommends that the NSTC be organized to pursue DARPA-like programs. It notes that, although looking at ways to incrementally improve leadership is not bad, the industry needs to take a moonshot approach to leapfrog current conventions and allow opportunities for breakthrough technology to keep the U.S. in a leadership position in the microelectronics market.

The Action Plan

The overarching goal of SCSP’s action plan is to “Chart a post–Moore’s Law future by catalyzing disruptive innovation via compute moonshots and build a flourishing atoms-to-architectures innovation pipeline that can develop, scale, and integrate novel materials and devices. In parallel, make key supporting moves to address enabling factors that make future U.S. and democratic leadership possible.”

The action plan recommends six broad proposals to:

  1. Launch: Scale emerging compute paradigms via national moonshot programs
  2. Organize: Close gaps in the microelectronics innovation ecosystem
  3. Research: Fund and attract microelectronics R&D
  4. Scale: Enable technologies for future compute and microelectronics
  5. Assure: Collaborate with international partners for secure microelectronics
  6. People: Cultivate, attract, and retain microelectronics talent

Let’s briefly review these six action items.

Launch: SCSP recommends that the NSTC look at how to successfully integrate the different forms of computing that exist, or that are emerging onto one platform, and make them seamlessly interoperable via what is termed hybrid computing. This would, for example, merge the current CMOS compute technology with quantum, superconducting, neuromorphic, and optical hardware and compute technologies, with the goal of addressing complex artificial intelligence (AI) problems. Some of the sub-goals in the launch phase are to create a 1 million Qbit fault-tolerant quantum computer by 2028; to improve compute efficiency by 1,000 times to 1 million times; and to lead in superconductor technology.

Organize: The proposal is to set up the NSTC with three primary focus areas:

  • The first area of focus is the recommendation to have the NSTC pursue DARPA-like programs. DARPA has been funding different semiconductor programs that have a longer view on technology development. The action request is that the NSTC is positioned and organized to ensure U.S. technological leadership in computing and microelectronics over a 20-year time horizon by executing national, bar-setting programs. This would enable the NSTC to be shielded from external pressure in setting its agenda and be given time to determine if the research will meet the desired goals.
  • The second focus is on how the NSTC must be able to pursue disruptive innovation without outside pressure. The suggestion is that the NSTC behave in some cases like a venture capitalist (VC), funding high-risk programs that may have a 20-year window of development. The report recognizes that to support this VC-like behavior, the NSTC should have an incubator function, where high-risk programs can be incubated and accelerated to help achieve success.
  • The third focus is how to fund the NSTC and the SCSP action items.

Research: The U.S. CHIPS Act is designed to provide a significant amount of funding over the next five years for the NSTC but leaves questions as to whether it is enough to fund a moonshot program and whether the funding would continue after the five years. While it’s not explicitly mentioned, the authors may well have had Sematech in the back of their minds, which received strong government support when first funded but quickly faded over time.

  • The first funding action item proposed is to make sure the NSTC is fueled past the 2027 time frame. Congress needs to put plans into place to keep funding the NSTC so that the U.S. can maintain technology leadership.
  • The second proposal is to create what the authors call a crowd-in industry R&D funding by improving the tax incentives so that companies realize R&D tax credits sooner and allow for capital equipment used for R&D to be expensed as well. With an extreme ultraviolet (EUV) stepper running in the $185M range, being able to expense the cost could help jump-start R&D spending.

Scale: The fourth action is how to scale the activities, which has a long list of proposals.

  • Unleash AI-powered chip design tools
  • Build digital twins for compute and microelectronics R&D
  • Scale the materials genome initiative for AI-enabled materials discovery
  • Reshape microelectronics fabrication via fab-in-a-box approaches
  • Pursue technological leadership in advanced packaging and chiplets
  • Unleash next-generation lithography by deepening public-private partnerships
  • Offer cryogenic refrigeration as a service

Some of these action items are somewhat self-explanatory. Cryogenic refrigeration as a service is needed to support quantum computing superconductors. Scaling the materials genome initiative for AI-enabled materials discovery would have a significant impact on the development of new materials that are needed for superconductors, as well as two-dimensional materials, to be used as gate or conductor material. The use of this concept could speed up development and adoption significantly. The fab-in-a-box action item, or developing additive manufacturing technology, would take 3D printing, or growing semiconductors to new levels, and have the potential to significantly reduce manufacturing costs. Next-generation lithography will require a collaborative effort and significant funding to develop the next source. The People’s Republic of China (PRC) is currently working on a particle accelerator that was first developed at Stanford. The recommendation is that the NCST use Department of Energy (DOE) National Laboratories’ particle accelerator technology to explore new sources and then create partnerships with industry to develop prototypes using the new source to leapfrog the Chinese development.

Assure: The fifth proposal is to consider how to secure microelectronics. The premise is that chips must be designed with security in mind. The plan proposes close collaboration with international chip partners to create secure by-design microelectronics so that security is built in, and chips and systems sold by these international partners would be considered secure. The action plan identifies serious concerns with trailing-edge chip production coming out of China. One is security; there is a concern that when the trailing-edge chips are sold outside of China, they could be enabled with spyware that could be used for cyber attacks. Another is the potential of selling chips at anti-competitive pricing and significantly increasing dependence on China for certain chip types. To combat the potential for saturating the market with legacy semiconductors, the SCSP proposes 1) developing critical infrastructure security standards with allies and partners; and 2) creating labeling and certification requirements for microelectronics used in the U.S. and allied critical infrastructure sectors. This would create a secure supply of legacy for the U.S. and its allies.

People: One of the key challenges for the domestic microelectronics space is having enough talent to run fabs. The reality is that working in VC community funding or on coding is more popular than the semiconductor industry. Because a considerable number of students studying in the microelectronics space are international, one key action item is to have Congress revise the visa program to help retain STEM PhDs and undergraduate students who have studied in the U.S. This would entice international students to stay and help grow the U.S. microelectronics industry instead of returning to their home country. It is suggested that the U.S. develop an innovator visa category for highly skilled internationals working in the microelectronics industry. It is suggested that the NSTC set up programs to nurture communities of engineering practice in emerging microelectronics paradigms. The goal is that this would create more resources for those communities that might already be working on a moonshot technology. And finally, scale the custom silicon effort for college student experiments. This would enable students to experiment freely with silicon design using AI tools to develop chips with new ideas for new applications.


The SCSP makes a compelling argument that the continued leadership of the U.S. in advanced computing and microelectronics is not assured. While it has set out its recommendations in its action plan, it acknowledges that success depends on many factors and efforts. The full plan is worth a read; you can find it here.